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T6A04A
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6A04A
Column and Row Driver LSI for a Dot Matrix Graphic LCD
The T6A04A is a driver for a small-to-medium-sized scale dot matrix graphic LCD. It includes the functions of the T9841B (column driver) and the T9842B (row driver). It has an 8-bit interface circuit and can be operated with an 80-Series MPU. It generates all the timing signals for the display with an on-chip oscillator. It receives 8-bit data from an MPU, latches the data to an on-chip RAM, and displays the image on the LCD (the data in the display RAM correspond to the dots on the display). The device has 120 column driver outputs and 64 row driver outputs enabling it to drive a 120-dot by 64-dot LCD. In addition, there are resistors to divide the bias voltage, a power supply op-amp, DC-DC converter (+5 V -5 V) and contrast control circuit, enabling the LCD to be driven by a single power supply. The device can be connected to another T6A04A to drive a 240-dot by 64-dot LCD.
Unit: mm T6A04A (UAW, 6NS) (UEM, 7NS) Lead Pitch IN 1.0 0.4 OUT 0.28 0.4
Please contact Toshiba or an authorized Toshiba dealer for information on package dimensions.
TCP (Tape Carrier Package)
Features
* * On-chip display RAM capacity Display RAM data (1) Display data = 1.................. LCD turns on. (2) Display data = 0.................. LCD turns off. * * * * * * * * * * * 1/64 duty cycle Word length of display data can be switched between eight bits and six bits according to the character font. LCD driver outputs Interface with 80-series MPU On-chip oscillator with one external resistor Low power consumption On-chip resistors to divide bias voltage, on-chip operational amplifier for LCD supply, on-chip DC-DC converter, on-chip contrast control circuit CMOS process Operating voltage Package : 4.5 to 5.5 V : TCP (tape carrier package) Operating voltage for LCD drive signal : VDD - VEE = 16.0 V (max) : 120 column driver outputs and 64 row driver outputs : 120 x 64 = 7.5 kbits
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T6A04A
Block Diagram
COM33 LCD DRIVE CIRCUIT (32) LCD DRIVE CIRCUIT (120) LATCH 120 DISPLAY RAM 120 64 = 7.5 kbits INPUT/OUTPUT GATE TIMING GENERATION X-COUNTER CIRCUIT Z-COUNTER 8 OSCILLATOR OP-AMP CONTROL REGISTER DISPLAY ON/OFF REGISTER BIT TRANSFER CIRCUIT 4 8 4 OUTPUT REGISTER 8 OUTPUT BUFFER INPUT/OUTPUT BUFFER PM CL FRM I/F CONTROL CIRCUIT M /STB EXP /RST D/I /WR /CE INPUT/OUTPUT BUFFER INPUT REGISTER 8 Y-ADDRESS COUNTER/DECODER 32-bit SHIFT REGISTER COM64 SEG1 SEG120
COM1
COM32
LCD DRIVE CIRCUIT (32)
32-bit SHIFT REGISTER
MPX
M/S
FS1 FS2
2
VLC1 VLC2 VLC3 VLC4 VLC5
OP-AMP (5) CONTRAST CONTROL REGISTER XY COUNTER SELECT REGISTER COUNTER UP/DOWN REGISTER Z-ADDRESS REGISTER
R1
R2
RESISTOR LADDERS
DECODER
3
3 5
MPX
VEE
CONTRAST CONTROL CIRCUIT
WORD LENGTH CONVERTER REGISTER
VIN
VOUT
DC-DC CONVERTER
INPUT/OUTPUT BUFFER
C1
C2
COMD SCLK OSC1 OSC2 /f
DB0 to DB7
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Pin Assignment
COM32
COM1 SEG1
T6A04A (top view)
SEG120 COM33
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 /RST /CE /WR D/I EXP M/S OSC2 OSC1 FS2 FS1 VDD /f PM fB fA Pf FRM M CL COMB VSS /STB VOUT C2 C1 VIN R2 R1 VEE VLC1 VLC2 VLC3 VLC4 VLC5
COM64
Note 1: The above diagram shows the pin configuration of the LSI chip; it does not show the configuration of the tape carrier package.
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Pin Functions
Pin Name SEG1 to SEG120 I/O Output Column driver output Row driver output COM1 to COM64 Output Disable expansion mode (EXP = L, M/S = H) (R) COM1 to COM64 are enabled. Enable expansion mode/master mode (EXP = H, M/S = H) (R) COM1 to COM32 are enabled and COM33 to COM64 are disabled. Enable expansion mode/slave mode (EXP = H, M/S = L) (R) COM1 to COM32 are disabled and COM33 to COM64 are enabled. Functions
Input/output for shift clock pulse CL I/O Master mode (M/S = H) (R) Output Slave mode (M/S = L) (R) Input
Input/output for frame signal M I/O Master mode (M/S = H) (R) Output Slave mode (M/S = L) (R) Input
Input/output for display synchronous signal FRM I/O Master mode (M/S = H) (R) Output Slave mode (M/S = L) (R) Input
Input/output system clock signal Pf, fA, fB I/O Master mode (M/S = H) (R) Output Slave mode (M/S = L) (R) Input
Input/output row signal data COMD I/O DB0 to DB7 I/O Master mode (M/S = H) (R) Output Slave mode (M/S = L) (R) Input
Data bus Input for data/instruction select signal
D/I
Input

D/I = H (R) indicates that the data on DB0 to DB7 is display data. D/I = L (R) indicates that the data on DB0 to DB7 is control data.
Input for write select signal /WR Input /WR = H (R) Read selected /WR = L (R) Write selected
Input for chip enable signal /CE Input /RST Input /WR = L (R) Data on DB0 to DB7 is latched on the rising edge of /CE. /WR = H (R) Data appears at DB0 to DB7 while /CE is Low.
Input for reset signal /RST = L (R) Reset state
Input for standby signal /STB Input FS1, FS2 Input Usually connected to VDD /STB = L (R) T6A04A is in standby state and cannot accept any commands or data. Column driver signal and row driver signal are at the VDD level
Input for frequency selection Input for expansion mode selection
EXP
Input

M/S = H (R) enables expansion mode. Two chips can be used together. M/S = L (R) disables expansion mode.
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Pin Name I/O Input for master/slave selection M/S Input OSC1, OSC2 3/4 M/S = H (R) T6A04A is master chip. M/S = L (R) T6A04A is slave chip. Functions
When using the internal clock oscillator, connect a resistor between OSC1 and OSC2. When using an external clock, connect the clock as input to OSC1 and leave OSC2 open. Input for LCD drive bias selection LCD drive bias selection is shown in the following table R2 0 0 1 1 R1 0 1 0 1 Bias 1/6 1/7 1/8 1/9
R1, R2
3/4
C1, C2 VIN VOUT VEE
3/4 3/4 3/4 3/4
Connected by a capacitor for DC-DC converter Input for DC-DC converter. Connect to VDD. DC-DC converter output Power supply for LCD driver circuit When using on-chip DC-DC converter, connect VEE to VOUT M/S = H (R) bias voltage output M/S = L (R) bias voltage input
Power supply for LCD driver circuit VLC1 to VLC5 3/4 VDD VSS PM /f 3/4 3/4 3/4 3/4
Power supply for logic circuit Ground: Reference Pre-frame signal for Toshiba T9841B Output system clock for Toshiba T9841B
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Function of Each Block
* Interface logic The T6A04A can be operated with an 80-Series MPU. Figure 1 shows an example of the interface.
A0 /IORQ /WR D0 to D7 /RESET D/1 /CE /WR <T6A04A> DB0 to DB7 /RST
Figure 1
* Input register This register stores 8-bit data from the MPU. The D/I signal distinguishes between command data and display data. * Output register This register stores 8-bit data from the display RAM. When display data is read, the display data specified by the address in the address counter is stored in this register. After that, the address is automatically incremented or decremented. Therefore, when an address is set, the correct data does not appear as the first data item that is read. The data in the specified address location appears as the second data item that is read. * X-address counter The X-address counter is a 64-up/down counter. It holds the row address of a location in the display RAM. Writing data to or reading data from the display RAM causes the X-address to be automatically incremented or decremented. * Y-(page) address counter The Y-(page) address counter is either a 15-up/down counter, when the word length is eight bits, or a 20-up/down counter, when the word length is six bits. It holds the column address of a location in the display RAM. Writing data to or reading data from the display RAM causes the Y-address to be automatically incremented or decremented. * Z-address counter The Z-address counter is a 64-up counter that provides the display RAM data for the LCD drive circuit. The data stored in the Z-address register is sent to the Z-address counter as the Z start address. For instance, when the Z start address is 32, the counter increments as follows: 32, 33, 34 ..., 62, 63, 0, 1, 2 ... 30, 31, 32. Therefore, the display start line is line 32 of the display RAM. * Up/down register The 1-bit datum stored in this register selects either Up or Down mode for the X-and Y-(page) address counters. * Counter select register The 1-bit datum stored in this register selects the X-address counter or Y-(page) address counter. * Display ON/OFF register This 1-bit register holds the display ON/OFF state. In the OFF state, the output data from the display RAM is cleared. In the ON state, the display RAM data is displayed. The display ON/OFF state does not affect the data in the display RAM. * Z-address register This 6-bit register holds the data which specifies the display start line. The data is loaded into the Z-address counter on the FRM signal. Using the Z-address register, vertical scrolling is possible.
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* Word length register The 1-bit datum stored in this register selects the word length: eight bits per word or six bits per word. * Word length change circuit This circuit is controlled by the word length register. when the word length is eight bits, data is transferred eight bits at a time. When the word length is six bits, the data transfer method is shown in Figure 2 as follows:
Display RAM * * D5 D4 D3 D2 D1 D0 * * D5 D4 D3 D2 D1 D0
Word length change circuit MPU D7 DB7 D6 DB6 D5 DB5 D4 DB4 D3 DB3 D2 DB2 D1 DB1 D0 DB0 0 DB7 0 DB6 D5 DB5
Word length change circuit D4 DB4 D3 DB3 D2 DB2 D1 DB1 D0 DB0
*: INVALID
Figure 2
* Oscillator The T6A04A includes an on-chip oscillator. When using this oscillator, connect an external resistor between OSC1 and OSC2, as shown in Figure 3. When using an external clock, connect the clock input to OSC1 and leave OSC2 open.
/STB Internal Circuit
OSC1
OSC2
Figure 3
* Timing generation circuit This circuit divides the signals from the oscillator and generates the display timing signals and the operating clock signal. * Shift register The T6A04A has two 32-bit shift registers. In disable expansion mode, both the shift registers are enabled. These two 32-bit shift registers can be combined to form a 64-bit shift register. In enable expansion mode the 32-bit shift register for COM1 to COM32 is enabled in master chip mode, and the 32-bit shift register for COM33 to COM64 is enabled in slave chip mode. * Latch circuit The latch circuit latches data from the display RAM on the rising edge of the CL signal.
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* Column driver circuit The column driver circuit consists of 120 driver circuits. One of the four LCD driving levels is selected by the combination of the M signal and the display data transferred from the latch circuit. Details of the column driver circuit are shown in Figure 4.
VLC5 VDD Display Data VLC3 VLC2 Vcoff SEG1 to SEG120
Vcon
M
Figure 4
* Row driver circuit The row driver circuit consists of 64 driver circuits. One of the four LCD driving levels is selected by the combination of the M signal and the data from the shift-register. Details of the row driver circuit are shown in Figure 5.
VDD VLC5 Shift Data VLC4 VLC1 Vroff COM1 to COM64
Vron
M
Figure 5
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T6A04A
* DC-DC converter The T6A04A has an on-chip DC-DC converter. When +5 V is applied to VIN, the DC-DC converter generates -5 V at VOUT. The voltage from VOUT will drop due to the load current for VEE. This characteristic is defined in "Electrical Characteristics". Normally the value of external capacitors is 1.0 mF; this value may need some adjustment according to the application. When the T6A04A is in standby state, VOUT = 0 V. See Figure 6.
Usually connected to VDD Usually connected to VEE
External capacitor C = 1.0 mF External capacitor C = 1.0 mF
C1 VIN DC-DC
C2 VOUT
Figure 6
When using an external power supply, input the voltage to VEE and leave the C1, C2 VOUT pins open.
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* Voltage divider resistors, contrast control circuit The T6A04A has on-chip resistors which include op-amps, that divide the bias voltage, and a contrast control circuit. The voltage bias is modified by the values of R1 and R2. One of four biases can be selected. These resistors and the contrast control circuit are shown in Figure 7 below.
= RB = 134 kW (typ.) RC = 10.1 kW (typ.) RB R2 Decoder R1 RB RB 5RB 4RB 3RB 2RB RC 2RC Contrast Control Register 4RC 8RC 16RC 32RC DB0 DB1 DB2 DB3 DB4 DB5 RB Voltage Follower Circuit VDD VLC1 VLC2 VLC3 VLC4 VLC5
VEE /STB Decoder DB7 DB6
Figure 7
* Op-amp, op-amp control register The T6A04A has five operational amplifiers which determine the LCD driving level. The power supplied by these op-amps is modified by the contents of the op-amp control register to match the LCD panel. The op-amp can also be controlled in such a way that it supplies full current on the rising edge of CL and a reduced current otherwise. To maintain good LCD contrast, connect a capacitor between the op-amp output and VDD. The value of the capacitor should normally be in the range 0.1 to 1.0 mF.
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* Display RAM The display RAM consists of 64 rows 120 columns for a total of 7680 cells. It is directly bit-mapped to the LCD. The relation between the display RAM and LCD is shown in Figure 8. When the word length is set to eight bits, the display RAM is arranged in 15 pages and each page contains 64 words. When the word length is set to six bits, the display RAM is arranged in 20 pages and each page contains 64 words. See Figure 8.
SEG120 PAGE14 PAGE18 PAGE19 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 1 0 SEG16 0 1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
COM1 COM2
SEG9 1 0
COM64
120 64 dot LCD
XAD0 1 X-Address XAD1 0
0 1
1 0
0 1
1 0
0 1
1 0
0 1
0 1
1 0
0 1
1 0
0 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB XAD63 LSB 120 64 bit DISPLAY RAM
Figure 8
(1) 8-bits-per-word mode
PAGE0 XAD0 XAD1 X-Address D7 D0 PAGE1 PAGE2 Y- (page) Address PAGE13
XAD62 XAD63
(2)
6-bits-per-word mode
PAGE0 XAD0 XAD1 X-Address D5 D0 PAGE1 PAGE2 Y- (page) Address
XAD62 XAD63
Figure 9 11 2002-03-06
T6A04A
Command Definitions
Command Name DPE 86E UDE CHE OPA1 OPA2 SYE SZE SXE SCE STRD DAWR DARD D/I 0 0 0 0 0 0 0 0 0 0 0 1 1 /WR 0 0 0 0 0 0 0 0 0 0 1 0 1 DB7 0 0 0 0 0 0 0 0 1 1 B DB6 0 0 0 0 0 0 0 1 0 1 8/6 D DB5 0 0 0 0 0 0 1 DB4 0 0 0 1 1 0 DB3 0 0 0 1 0 1 DB2 0 0 1 * * * DB1 1 0 1/0 * 1/0 1/0 DB0 1/0 1/0 1/0 * 1/0 1/0 Function Display ON (1)/OFF (0) Word Length: 8 bits (1)/6 bits (0) Counter Select : DB1 Y (1)/X (0) Mode Select : DB0 UP (1)/DOWN (0)
Test Mode Select Op-amp Power Control 1 Op-amp Power Control 2 Y-(page) Address Set Z-Address Set X-Address Set Contrast Set Status Read Display Data Write Display Data Read
Y-(page) Address (0 to 19) Z-Address (0 to 63) X-Address (0 to 63) CONTRAST CONTROL (0 to 63) R 0 0 Y/X U/D
Write Data Read Data
*: INVALID
*
Display ON/OFF select (DPE)
/WR 0 0
D/I 0 0
DB7 0 0
DB6 0 0
DB5 0 0
DB4 0 0
DB3 0 0
DB2 0 0
DB1 1 1
DB0 1 0 Display ON (03H) Display OFF (02H)
This command turns display ON/OFF. It does not affect the data in the display RAM. Note 2: An L input on /RST turns display OFF.
*
Word length 8 bits/6 bits select (86E)
/WR 0 0
D/I 0 0
DB7 0 0
DB6 0 0
DB5 0 0
DB4 0 0
DB3 0 0
DB2 0 0
DB1 0 0
DB0 1 0 8 Bits/Word Mode (01H) 6 Bits/Word Mode (00H)
This command sets the word length for display RAM data to eithers six bits or eight bits. Note 3: An L input on /RST sets the word length to eight bits per word.
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* X/Y (page) counter, up/down mode select (UDE)
/WR 0 0 0 0
D/I 0 0 0 0
DB7 0 0 0 0
DB6 0 0 0 0
DB5 0 0 0 0
DB4 0 0 0 0
DB3 0 0 0 0
DB2 1 1 1 1
DB1 0 0 1 1
DB0 0 1 0 1 X-Counter/Down Mode (04H) X-Counter/Up Mode (05H) Y-Counter/Down Mode (06H) Y-Counter/Up Mode (07H)
This command selects the counter and the up/down mode. For instance, when X-counter/up mode is selected, the X-address is incremented in response to every data read and write. However, when X-counter/up mode is selected, the address in the Y-(page) counter will not change. Hence the Y-address must be set (with the SYE command) before it can be changed. Note 4: An L input to /RST sets the Y-counter to up mode.
*
Test mode select (CHE)
/WR 0
D/I 0
DB7 0
DB6 0
DB5 0
DB4 1
DB3 1
DB2 *
DB1 *
DB0 *
*: INVALID
This command selects the test mode. Do not use this command.
*
Set Y-(page) address (SYE)
/WR 0
D/I 0
DB7 0
DB6 0
DB5 1
DB4 A
DB3 A
DB2 A
DB1 A
DB0 A
Range: 8-bit/Word: 20H to 2EH (page 0 to page 14) 6-bit/Word: 20H to 33H (page 0 to page 19) When operating in 8-bits-per-word mode, this command selects one of the 15 pages from the display RAM. (Do not try to select a page outside this range.) When operating in 6-bits-per-word mode, this command selects one of the 20 pages from the display RAM. Note 5: An L input to /RST sets the Y-address to page 0.
*
Set Z-address (SZE)
/WR 0
D/I 0
DB7 0
DB6 1
DB5 A
DB4 A
DB3 A
DB2 A
DB1 A
DB0 A
Range: 40H to 7FH (ZAD0 to ZAD63) This command sets the top row of the LCD screen, irrespective of the current X-address. For instance, when the Z-address is 32, the top row of the LCD screen is address 32 of the display RAM, and the bottom row of the LCD screen is address 31 of the display RAM. Note 6: An L input to /RST sets the Z-address to 0.
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* Set X-address (SXE)
/WR 0 D/I 0 DB7 1 DB6 0 DB5 A DB4 A DB3 A DB2 A DB1 A DB0 A
Range: 80H to BFH (XAD0 to XAD63) This command sets the X-address (in the range 0 to 63). An L input to /RST sets the X-address to 0. * Set contrast (SCE)
/WR 0 D/I 0 DB7 1 DB6 1 DB5 A DB4 A DB3 A DB2 A DB1 A DB0 A
Range: C0H to FFH This command sets the contrast for the LCD. The LCD contrast can be set in 64 steps. The command C0H selects the brightest level; the command FFH selects the darkest. * Op-amp control 1 (OPA1)
/WR 0 D/I 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 * DB1 A DB0 A
*: INVALID
Range: 10H to 13H (when DB2 = 0) This command sets the power supply strength for the operational amplifier. This command selects one of four levels. The command 10H selects the lowest power supply strength and the command 13H selects the maximum strength. Note 7: An L input to /RST sets the op-amp power supply strength to the lowest level. * Op-amp control 2 (OPA2)
/WR 0 D/I 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 * DB1 A DB0 A
*: INVALID
Range: 08H to 0BH (when DB2 = 0) This command enhances the power supply strength of the operational amplifier over a short period from the rising edge of CL. This command selects one of four levels of strength. Note 8: An L input to /RST sets t to 0 for op-amp. See Figure 10.
T CL (1) When this command is 08H (2) When this command is 09H (3) When this command is 0AH (4) When this command is 0BH t=0 t t t t/T = 1/12 t/T = 1/6 t/T = 1/3
The amplifier's strength is enhanced over the period denoted by , starting on the rising edge of CL.
Figure 10 14 2002-03-06
T6A04A
* Status read (STRD)
/WR 1
D/I 0
DB7 B
DB6 8/6
DB5 D
DB4 R
DB3 0
DB2 0
DB1 Y/X
DB0 U/D
B (busy)
: When B is 1, the T6A04A is executing an internal operation and no instruction can be accepted except STRD. When B is 0, the T6A04A can accept an instruction.
8/6 (word length) : When 8/6 is 1, the word length of the display data is eight bits per word. When 8/6 is 0, the word length of the display data is six bits per word. D (display) R (reset) Y/X (counter) U/D (up/down) : When D is 1, display is ON. When D is 0, display is OFF. : When R is 1, the T6A04A is in reset state. When R is 0, the T6A04A is in operating state. : When Y/X is 1, the Y counter is selected. When Y/X is 0, the X counter is selected. : When U/D is 1, the X and Y counters are in up mode. When U/D is 0, the X and Y counters are in down mode.
*
Write/read display data (DAWR/DARD)
/WR 0 1
D/I 1 1
DB7 D D
DB6 D D
DB5 D D
DB4 D D
DB3 D D
DB2 D D
DB1 D D
DB0 D D DAWR: Display Data Write DARD: Display Data Read
The command DAWR writes the display data to the display RAM. The command DARD outputs the display data from the display RAM. However, when a data read is executed, the correct data does not appear on the first data reading. Therefore, ensure that the T6A04A performs a dummy data read before reading the actual data.
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Function Description
* X-address counter and Y-(page) address counter Figure 11-1 shows a sample operation involving the X-address counter. After Reset is executed, the X-address (XAD) becomes 0, then X-counter/up mode is selected. Next, the X-address is set to 62 using the SXE command. After data has been written or read, the X-address is automatically incremented by 1. After X-counter/down mode has been selected and data has been written or read, the X-address is automatically decremented by 1. When the X-counter is selected, the Y-counter is not incremented or decremented.
Reset UDE = 05H SXE = BEH DAWR DAWR DAWR DAWR
XAD = 0 X-Counter/Up Mode X-Address Set XAD = 62 Data Write XAD = 63 XAD = 0 XAD = 1 XAD = 2
UDE = 04H DAWR DAWR DAWR
X-Counter/Down Mode
XAD = 1 XAD = 0 XAD = 63
Figure 11-1
Figure 11-2 shows a sample operation involving the Y-address counter in 8-bit word length mode. After Reset is executed, the Y-(page) address (page) becomes 0, then Y-(page) counter/up mode and 8-bit word length mode are selected. After data has been written or read, the Y-(page) address counter is automatically incremented by 1. After Y-(page) counter/down mode has been selected and data has been written or read, the Y-(page) address is automatically decremented by 1. When the Y-(page) counter is selected, the X-counter is not incremented or decremented.
Reset UDE = 07H 86E = 01H SYE = 2DH DAWR DAWR DAWR
Page = 0 Y-counter/Up mode Word length 8 Bits/Word Y-address Set Page = 13 Page = 14 Page = 0 Page = 1
DAWR UDE = 06H DAWR DAWR DAWR
Page = 2 X-Counter/Down Mode
Page = 1 Page = 0 Page = 14
Figure 11-2
When operating in 6-bit word length mode, the Y-(page) address counter can court up to 19. If Page = 18 in up mode, after data has been written or read, the Y-(page) address (page) becomes 0. If Page = 0 in down mode, after data has been written or read, the Y-(page) address (page) becomes 18.
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* Data read When reading data, there are some cases when dummy data must be read. This is because when the data read command invoked, the data pointed to by the address counter is transferred to the output register; the contents of the output register are then transferred by the next data read command. Therefore when reading data straight after power-on or straight after an address-setting command, such as SYE or SXE, a dummy data read must be performed. See Figure 12.
Power on SYE = 20H SXE = 80H UDE = 05H Dummy Read DARD 0 DARD 1 DARD 0 DARD 1 DARD 2
DARD 0 DARD 1 SYE = 21H Dummy Read
Figure 12
* Reset function When /RST = L, the reset function is executed and the following settings are mode. (3) Display .....................................OFF (4) Word length..............................8 bits/word (5) Counter mode...........................Y-counter/up mode (6) Y-(page) address.......................Page = 0 (7) X-address .................................XAD = 0 (8) Z-address..................................ZAD = 0 (9) Op-amp1 (OPA1) ......................min (10) Op-amp2 (OPA2) ......................min * Standby function When /STB = L, the T6A04A is in standby state. The internal oscillator is stopped, power consumption is reduced, and the power supply level for the LCD (VLC1 to VLC5) becomes VDD. * Busy flag When the T6A04A is executing an internal operation (other than the STRD command), the busy flag is set to logical H. The state of the busy flag is output in response to the STRD command. While the busy flag is H, no instruction can be accepted (except the STRD command). The busy state period (T) is as follows. fosc: Frequency of OSC1 2/fosc < T = 4/fosc [seconds] =<
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* Oscillation frequency The frequency select pins (FS1 and FS2), are used to set the relation between the oscillation frequency (fOSC) and frame frequency (fM), as shown in the table below.
Rf (kW) 1000 480 105 50 fOSC (kHz) 26.88 53.76 215.00 430.10 f/f (kHz) 13.44 26.88 107.50 215.00 fFRM (Hz) 70 70 70 70 fM (Hz) 35 35 35 35 FS1 0 1 0 1 FS2 0 0 1 1
Note 9: The resistance values are typical values. The oscillation frequency depends on how the device is mounted. It is necessary to adjust the oscillation frequency to a target value.
*
Expansion function The T6A04A's expansion function, allows two, T6A04As to drive an LCD panel of up to 240 by 64 dots. The table below shows the functions which can be selected with the M/S and EXP pins.
M/S H H EXP Two-chip mode (enable expansion mode) Master chip COM1 to COM32 are available. L Two-chip mode (enable expansion mode) Slave chip COM33 to COM64 are available. Timing signals and power voltage are supplied from master chip. Do not select.
L
Single-chip mode (disable expansion mode) COM1 to COM32 are available.
Figures 13-1 and -2 illustrate application examples of disable expansion mode and enable expansion mode. Enable Expansion Mode (two-chip mode) As shown in Figure 13-2, and Figure 14 the master chip supplies the LCD drive signals and power voltage to the slave chip (the oscillator, the timing circuits, op-amp and contrast control circuit are disabled). COM1 to COM32 of the master chip and COM33 to COM64 of the slave chip are available (COM33 to COM64 of the master chip and COM1 to COM32 of the slave chip are disabled). The T9841B is available as an expansion driver for the T6A04A (a T6A04A and T9841B can drive a 200 64-dot LCD panel). (1) Disable expansion mode
120 dots 32 dots 32 dots COM33 to 64 COM32 Out 32 32-bit SR SEG1 to 120 SEG 120 Out 120 RAM 120 64 Cell COM32 Out 32 32-bit SR COM1 to 32
Figure 13-1
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T6A04A
(2) Expansion mode
120 dots 120 dots 32 dots 32 dots COM33 to 64 A COM Output COM fB fA SEG 120 Out Slave Chip Pf FRM B COM Output (disable) M CL C COM Output (disable) CL M SEG 120 Out Master chip FRM Pf fA D COM Output fB COMD COM1 to 32
Figure 13-2
MS = L 0.1 mF Op-Amp
MS = H Op-Amp
VLC1 Slave VLC2 VLC3 VLC4 Contrast Control VLC5 VEE DC-DC Converter VOUT
VLC1 Master Contrast Control DC-DC Converter VOUT VLC2 VLC3 VLC4 VLC5 VEE
Figure 14
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T6A04A
LCD Driver Waveform
fA /f
CL 64 FRM PM M VDD V1 COM1 V4 V5 V1 COM2 to COM64 V4 V5 VDD V2 SEG1 to SEG120 V3 V5 ON OFF ON OFF V3 V5 VDD V2 V3 VDD V3 VDD V4 V5 VDD V1 V4 VDD V1 V1 V4 V4 V4 VDD V5 V1 1 2 3 64 1 2 3 64 1
LCD driver timing chart (1/64 duty)
Absolute Maximum Ratings (Ta = 25C)
Characteristics Supply voltage (1) Symbol VDD (Note 10) VLC1, 2, 3, 4, 5 Supply voltage (2) VEE (Note 12) Input voltage Operating temperature Storage temperature VIN (Note 10, 11) Topr Tstg -0.3 to VDD + 0.3 -20 to 75 -55 to 25 V C C VDD - 18.0 to VDD + 0.3 V Rating -0.3 to 7.0 Unit V
Note 10: Referenced to VSS = 0 V Note 11: Applies to all data bus pins and input pins except VEE, VLC1, VLC2, VLC3, VLC4 and VLC5. Note 12: Ensure that the following condition is always maintained. VDD > VLC1 > VLC2 > VLC3 > VLC4 > VLC5 > VEE = = = = = =
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T6A04A
Electrical Characteristics
DC Characteristics
Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V 10%, VLC5 = 0 V, Ta = -20 to 75C)
Characteristics Operating supply (1) Operating supply (2) H level L level H level L level H level L level H level L level Symbol VDD VLC5 VEE VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 Rcol Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition 3/4 3/4 3/4 3/4 3/4 3/4 IOH = -400 mA IOL = 400 mA IOH = -205 mA IOL = 1.6 mA VDD - VLC5 = 11.0 V Load current = 100 mA VDD - VLC5 = 11.0 V Load current = 100 mA Min 4.5 VDD - 16.0 0.7 VDD 0 2.2 0 VDD - 0.4 0 2.4 0 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 5.5 VDD - 4.0 VDD 0.3 VDD VDD 0.8 VDD 0.4 VDD 0.4 7.5 V V Unit V V PIN Name VDD, VIN VEE, VLC5 M/S, EXP, R1, R2, CL, M, FRM, fA, fB, COMD, FS1, FS2, Pf DB0 to DB7, D/I, /WR, /CE, /RST, /STB CL, M, FRM, Pf, COMD, fA, fB D/I, /WR, /CE, DB0 to DB7, /RST, /STB SEG1 to SEG120 COM1 to COM64 M/S, EXP, R1, R2, CL, M, FRM, D/I, /WR, COMD, /CE, DB0 to DB7, /STB, /RST, FS1, FS2, Pf, fA, fB /f OSC1 OSC1 VDD VDD VDD VDD VOUT
Input voltage (1)
Input voltage (2) Output voltage (1) Output voltage (2)
V
V
Column output resistance
kW
Row output resistance
Rrow
3/4
3/4
3/4
1.5
kW
Input leakage
IIL
3/4
VIN = VDD to GND
-1
3/4
1
mA
Operating freq. External clock freq. External clock duty External clock rise/fall time Current consumption (1) Current consumption (2) Current consumption (3) Output voltage
f fex fduty tr/tf IDD1 IDD2 IDDSTB Vo
3/4 3/4 3/4 3/4 3/4 3/4 3/4 1
3/4 3/4 3/4 3/4 (Note 13) (Note 14) (Note 15) (Note 16)
10 20 45 3/4 3/4 3/4 -1 -4.0
3/4 3/4 50 3/4 850 950 3/4 -4.2
250 500 55 50 1400 1600 1 3/4
kHz kHz % ns mA mA mA V
Note 13: VDD = 5.0 V 10%, VEE = VOUT (from DC-DC converter) Master mode, no data access Rf = 47 kW, no load 1/9 bias, FS1, 2 = H, op-amp strength at minimum level Note 14: VDD = 5.0 V 10%, VEE = VOUT (from DC-DC Converter) Master mode, data access cycle f/CE = 1 MHz Rf = 47 kW, No load 1/9 bias, FS1, 2 = H, op-amp strength at minimum level Note 15: VDD = 5.0 V 10%, VDD - VEE = 16 V Master mode, /STB = L Note 16: VIN = 5.0 V, ILoad = 500 mA, VEE = -5.0 V (external power supply) C1 - C2 = 1.0 mF, VIN - VOUT = 1.0 mF, R = 47 kW, Ta = 25C
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T6A04A
Test Circuit 1.
VDD OSC1 VIN R OSC2 C1 C C2 VOUT VEE VSS C R = 47 kW C = 1.0 mF ILoad ILoad = 500 mA EXTERNAL POWER SUPPLY
AC Characteristics
D/I VIH2 VIL2 VIH2 VIL2 tAH /WR VIL2 tAS VIH2 VIL2 tEf Data Write tDD Data Read PWEL VIH2 VIL2
tAH tEr
/CE
tDS VIH2 VIL2
tDHW VIH2 VIL2
Valid Data tDHR Valid Data tcycE
VOH2 VOL2
VOH2 VOL2
Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V 10%, Ta = -20 to 75C)
Characteristics Enable cycle time Enable pulse width Enable rise/fall time Address set-up time Address hold time Data set-up time Data hold time Data delay time Data hold time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD (Note 17) tDHR (Note 17) 10 3/4 ns Min 500 220 3/4 40 0 60 10 3/4 Max 3/4 3/4 20 3/4 3/4 3/4 3/4 200 Unit ns ns ns ns ns ns ns ns DB0 to 7 C R D
Load Circuit
VDD RL D D D
RL = 2.4 kW R = 11 kW C = 130 pF (including wiring capacitance) D = 1S1588
Note 17: With load circuit connected
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T6A04A
Application Circuit
(1)
T6A04A single-chip mode
*
Oscillation frequency is at a minimum.
*
LCD drive bias is 1/9.
*
DC-DC converter is used.
120 64-dot LCD
COM1 to COM32 DB0 to DB7
SEG1 to SEG120
COM33 to COM64 VLC1 VLC2
VCC
D0 to D7 /CE D/I /WR /RST /STB FS1 FS2 M/S EXP R1 R2 VSS VDD T6A04A
/IORQ
A1
VLC3 VLC4 VLC5 OSC1 OSC2 VIN VOUT VEE C1 C2 0.1 mF
DECODER
An
MPU
A0
/WR
/RESET
GND 0.1 mF VCC
1.0 mF
1.0 mF
RESET CIRCUIT
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T6A04A
Application Circuit
(2)
T6A04A two-chip mode
*
Oscillation frequency is at a minimum.
*
LCD drive bias is 1/9.
*
DC-DC converter is used.
/IORQ 240 64-dot LCD
/CE1
A1
/CE2
DECODER
An
MPU
A0
/WR COM1 to COM32 COM33 to COM64 SEG1 to SEG120 SEG1 to SEG120
D0 to D7
/RESET
OSC2 COMD C2 OSC1 COMD
C2 1.0 mF C1 T6A04A (slave) VEE VOUT VIN FRM M FS1 M/S VDD VLC2 VLC4 Pf /STB FS2 EXP R1 R2 VSS VLC3 VLC5 fA fB VLC1 CL /RST VCC 1.0 mF
OSC1 VCC /CE VEE VOUT VIN D/I /WR DB0 to DB7 FRM M CL
C1
OSC2
/CE
T6A04A (master)
D/I
/WR
DB0 to DB7
/RST
FS1 M/S VLC4 VDD VLC2 Pf /STB FS2 EXP R1 R2 VSS VLC3 VLC5 fA fB VLC1
RESET CIRCUIT VCC 0.47 mF
0.1 mF
GND
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T6A04A
RESTRICTIONS ON PRODUCT USE
000707EBE
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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